Demand for integrated circuits (ICs) in portable electronic applications has motivated energy-efficient transistors. It is advantageous to reduce the operating voltage of transistors required to achieve a threshold minimum on/off drain current ratio. Subthreshold slope (SS) (expressed in mV/decade) characterizes a gate voltage required to change a drain current by one order of magnitude. In traditional FET technologies, SS has a thermal limit of approximately 60 mV/dec at room temperature (20° C.). Recently, in an effort to improve SS beyond 60 mV/dec, there has been renewed interest in ferroelectric FETs that employ a ferroelectric material (e.g., BaTiO3) within a gate stack. Internal polarization of the ferroelectric may act to “step-up” the gate potential across the ferroelectric layer to a semiconductor channel of the transistor, to increase effective capacitance and a lower operating voltage. Because of effective capacitance is increased, such devices are sometimes described as displaying a “negative capacitance effect.” Ferroelectric films however remain difficult to grow and have thus far have needed to be more than 100 nm thick to display a negative capacitance effect.
III-N heterostructure field effect transistors (HFET), such as high electron mobility transistors (HEMT) and metal oxide semiconductor (MOS) HEMT, employ a semiconductor heterostructure with one or more heterojunction, for example at an interface of a GaN semiconductor and another III-N semiconductor alloy, such as AlGaN or AlInN. GaN-based HFET devices benefit from the relatively wide bandgap (˜3.4 eV), enabling higher breakdown voltages than Si-based MOSFETs. III-N HFETs that display steeper subthreshold swings would advantageously improve power efficiency of such devices for mobile applications.